Semiconductor package with die stacked on surface mounted devices

ABSTRACT

One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.

BACKGROUND Technical Field

Embodiments of the present disclosure are directed to semiconductorpackages and methods in which one or more electrical components arepositioned between a semiconductor die and a surface of a substrate.

Description of the Related Art

Semiconductor packages, such as system in package (SiP) devices come inmany forms, including ball grid array (BGA) packages and land grid array(LGA) packages. BGA packages generally include an array of solder ballson an underside of a substrate in the package, which are used toelectrically couple the package to a printed circuit board (PCB).Similarly, LGA packages generally include an array of contacts on anunderside of a substrate in the package, which are used to electricallycouple the package to a PCB.

BGA and LGA packages are typically limited in terms of space, which inturn limits a number of components that can be integrated in suchpackages. For example, such packages typically include a top metal layeron which a semiconductor die, wire bonds, signal routing paths, groundplanes, a metal lid and other components are disposed. The top metallayer thus has very little, if any, available space for additionalcomponents, e.g., surface mounted components, to be integrated in thepackage. The bottom metal layer of such packages is similarly spacelimited, as the bottom metal layer is typically dedicated for connectingthe package to a PCB through either the solder balls (e.g., in BGApackages) or lands (e.g., as in LGA packages).

Miniaturization of semiconductor packaging is a continuing trend in theindustry; however, package miniaturization generally does not allow foran increase in integration of components in such packages, since packagesize generally increases as more components are integrated in thepackage. More particularly, a surface area or footprint of the packagetypically increases by integrating surface mounted devices on the toplayer of the package. An alternative integration technique is to embedone or more electrical components in the substrate of the package;however, this technique may be less desirable due to added expense interms of manufacturing yield.

BRIEF SUMMARY

Embodiments of the present disclosure are generally directed tosemiconductor packages and methods in which one or more electricalcomponents are positioned between a semiconductor die and a surface of asubstrate.

In some embodiments, one or more surface mounted devices (SMDs) arepositioned on a surface of a substrate, and the semiconductor die ispositioned on or over the one or more SMDs, with an active surface ofthe semiconductor die facing away from the SMDs. That is, a non-activesurface of the semiconductor die faces the SMDs. One or more wire bondsare connected between the active surface of the semiconductor die andelectrical contacts on the substrate.

In some embodiments, a cavity may be formed in a substrate, such thatthe cavity extends through an upper surface of the substrate. One ormore SMDs are positioned in the cavity, and a semiconductor die ispositioned over the SMDs, with the active surface of the semiconductordie facing away from the SMDs.

In some embodiments, one or more SMDs and one or more solder balls arepositioned on a surface of a substrate. A semiconductor die ispositioned on or over the SMDs and solder balls, and the solder balls atleast partially support the semiconductor die. The active surface of thesemiconductor die may be facing away from the surface of the substrate,and wire bonds may be formed that connect the semiconductor die toelectrical contacts of the substrate.

In some embodiments, a spacer, such as a dummy die, is positioned on asurface of the substrate. A semiconductor die is positioned on thespacer, and the spacer separates the semiconductor die from the surfaceof the substrate. The spacer has a smaller surface area than does thesemiconductor die, and one or more gaps are thus formed between thespacer and the semiconductor die. One or more SMDs may thus bepositioned on the surface of the substrate in the gaps adjacent to thespacer, with the SMDs being between the semiconductor die and thesubstrate. The active surface of the semiconductor die may be facingaway from the spacer, and one or more wire bonds may be connectedbetween the active surface of the semiconductor die and electricalcontacts on the substrate.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor package including asemiconductor die attached to a plurality of electrical components byglue that encapsulates the electrical components, in accordance with oneor more embodiments of the present disclosure.

FIG. 2 is a cross-sectional view of a semiconductor package including asemiconductor die attached to a plurality of electrical components thatare molding underfill, in accordance with one or more embodiments.

FIG. 3 is a cross-sectional view of a semiconductor package includingelectrical components positioned in a cavity of a substrate, and asemiconductor die positioned on the electrical components, in accordancewith one or more embodiments.

FIG. 4 is a cross-sectional view of a semiconductor package including asemiconductor die spaced apart from a substrate by solder balls, and aplurality of electrical components positioned between the die and thesubstrate, in accordance with one or more embodiments.

FIG. 5 is a cross-sectional view of a semiconductor package including asemiconductor die spaced apart from a substrate by a spacer, and aplurality of electrical components positioned between the die and thesubstrate, in accordance with one or more embodiments.

FIGS. 6A-6D are cross-sectional views illustrating a method ofmanufacturing the semiconductor package shown in FIG. 1, in accordancewith one or more embodiments.

FIGS. 7A-7C are cross-sectional views illustrating a method ofmanufacturing the semiconductor package shown in FIG. 3, in accordancewith one or more embodiments.

DETAILED DESCRIPTION

In the following description, certain specific details are set forth inorder to provide a thorough understanding of various disclosedembodiments. However, one skilled in the relevant art will recognizethat embodiments may be practiced without one or more of these specificdetails, or with other methods, components, materials, etc. In otherinstances, well-known structures associated with leadframes and chippackaging have not been shown or described in detail to avoidunnecessarily obscuring descriptions of the various embodiments providedherein.

Unless the context requires otherwise, throughout the specification andclaims that follow, the word “comprise” and variations thereof, such as“comprises” and “comprising” are to be construed in an open, inclusivesense, that is, as “including, but not limited to.” Further, the terms“first,” second,” and similar indicators of sequence are to be construedas being interchangeable unless the context clearly dictates otherwise.

Reference throughout the specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment. Thus, the appearance of the phrases “in oneembodiment” or “in an embodiment” in various places throughout thespecification are not necessarily all referring to the same embodiment.Furthermore, the particular features, structures, or characteristics maybe combined in any suitable manner in one or more embodiments of thepresent disclosure.

As used in the specification and the appended claims, the singular forms“a,” “an,” and “the” include plural referents unless the context clearlydictates otherwise. It should also be noted that the term “or” isgenerally employed in its broadest sense, that is, as meaning “and/or”unless the context clearly dictates otherwise.

In various embodiments, the present disclosure provides semiconductorpackages having one or more electrical components, such as surfacemounted devices, positioned between a semiconductor die and a surface ofa substrate. The substrate may be a BGA substrate, i.e., with an arrayof solder balls on an underside of the substrate. In other embodiments,the substrate may be a LGA substrate, i.e., with an array of contacts orleads on an underside of the substrate. The electrical components may bepositioned in a cavity of the substrate, or may be positioned on anupper surface of the substrate. The semiconductor die may be supportedby the electrical components and/or by one or more supportingstructures, such as solder balls, a dummy die, or any spacer. In someembodiments, the semiconductor die is attached to the electricalcomponents by glue, while in other embodiments, the semiconductor diemay be secured in place over the electrical components by anencapsulation layer, such as a molding compound.

FIG. 1 shows a cross-sectional view of a semiconductor package 10, inaccordance with one or more embodiments of the present disclosure. Thepackage 10 includes a substrate 12, one or more electrical components14, and a semiconductor die 16.

The substrate 12 has a first surface 13 (e.g., an upper surface) and asecond surface 15 (e.g., a lower surface) that is opposite to the firstsurface. The substrate 12 includes electrical contacts 18, or pads, onthe first surface 13, and electrical contacts 20, such as solder balls,on the second surface 15. In the illustrated embodiment, the package 10is a ball grid array (BGA) package having an array of solder balls whichserve as the electrical contacts 20 on the underside of the package 10;however, it should be readily appreciated that in other embodiments, theelectrical contacts 20 may be, for example, lands in a land grid array(LGA) package.

The substrate 12 may be any substrate suitable for electrically couplingelectrical components or devices on the first surface 13 to one or moreother electrical components or devices on the first surface 13 and/or toone or more of the electrical contacts 20 on the second surface 15 ofthe substrate 12. More particularly, the substrate 12 may include avariety of conductive paths that electrically couple one or more of theelectrical contacts 18 on the first surface 13 to one or more of theelectrical contacts 20 on the second surface 15. The substrate 12 mayfurther include conductive paths that electrically couple one or more ofthe electrical contacts 18 on the first surface 13 to other electricalcontacts 18 on the first surface 13. The conductive paths may include,for example, one or more vias or conductive through-holes that extendthrough the substrate 12, laterally extending wiring paths that areformed in one or more inner layers of the substrate 12 (i.e., layersthat are between the first and second surfaces 13, 15), conductivesignal paths that are formed on the first surface 13, or any otherconductive path on or in the substrate 12. In one or more embodiments,the substrate 12 is a multi-layer printed circuit board (PCB) having avariety of conductive paths formed between the electrical contacts 18 onthe first surface 13 and the electrical contacts 20 on the secondsurface 20. Such a multi-layer PCB may further include conductive pathsbetween one or more of the electrical contacts 18 on the first surface13 and other electrical contacts 18 on the first surface 13.

One or more electrical components 14 are positioned on and electricallycoupled to the first surface 13 of the substrate 12. For example, theelectrical components 14 may be electrically coupled to respectiveelectrical contacts 18 by a conductive material, such as solder paste22.

The electrical components 14 may be any surface mount devices (SMDs)that can be mounted on a surface (e.g., on the first surface 13 of thesubstrate 12) using surface mount technology (SMT). In one or moreembodiments, the electrical components 14 may be passive electricalcomponents, including resistors, capacitors, and inductors. As shown inFIG. 1, the electrical components 18 may be two-terminal components;however, it should be readily appreciated that three or more terminalcomponents may be included as electrical components 14 in variousembodiments. Moreover, the electrical components 14 on the first surface13 of the substrate 12 may have various different dimensions. Forexample, some of the electrical components 14 may have differentheights, widths, and/or thicknesses.

As shown in FIG. 1, an adhesive, such as glue 24, may cover one or moreof the electrical components 14. The glue 24 may be, for example, a globtop, which forms an electrically insulating protective dome over theelectrical components 14. The semiconductor die 16 is positioned on theglue 24 and is mechanically attached to the underlying electricalcomponents 14 by the glue 24. As shown in FIG. 1, the glue 24 maysubstantially surround or encapsulate the electrical components 14 thatare positioned between the semiconductor die 16 and the substrate 12.The semiconductor die 16 is thus supported in the package 10 by theelectrical components 14. As noted previously, the electrical components14 may have various different dimensions, including height; however, inthe implementation shown in FIG. 1, it may be desirable that theelectrical components 14 that underlie the semiconductor die 16 have asubstantially same height in order to provide a relatively uniform, flatsupporting surface for placement of the semiconductor die 16.

Additional electrical components 14 may be positioned on the firstsurface 13 of the substrate 12 and spaced apart laterally from theelectrical components 14 that are positioned beneath the semiconductordie 16, as shown.

The semiconductor die 16 is made from a semiconductor material, such assilicon. The semiconductor die 16 includes an active surface 17 thatincludes one or more electrical components, such as integrated circuits.The integrated circuits may be analog or digital circuits implemented asactive devices, passive devices, conductive layers, and dielectriclayers formed within the semiconductor die 16 and electricallyinterconnected according to the electrical design and function of thesemiconductor die 16. In various implementations, the semiconductor die16 may include electrical components and/or circuitry that form anapplication specific integrated circuit (ASIC).

Conductive wires 26 or wire bonds electrically couple the active surface17 of the semiconductor die 16 to the substrate 12. For example, theconductive wires 26 may electrically couple respective bond pads (notshown) on the active surface 17 of the semiconductor die 16 torespective electrical contacts 18 on the first surface 13 of thesubstrate 12.

An encapsulation layer 30 is formed over the semiconductor die 16, andcovers the semiconductor die 16 and the conductive wires 26 to form apackage body. The encapsulation layer 30 extends from some height overthe active surface 17 of the semiconductor die 16 to at least the firstsurface 13 of the substrate 12, and substantially fills any spacestherebetween, as shown. In some embodiments, the encapsulation layer 30may further be provided on side surfaces of the substrate 12 and/or onthe second surface 15 of the substrate 12, e.g., between the electricalcontacts 20. The encapsulation layer 30 is an electrically insulatingmaterial that protects the electrical components 14, semiconductor die16, conductive wires 26, first surface 13 of the substrate 12, and anyother electrical components or wiring from damage, such as corrosion,physical damage, moisture damage, or the like. In one or moreembodiments, the encapsulation layer 30 is a molding compound, which mayinclude, for example, a polymer resin. The electrical components 14 thatare between the semiconductor die 16 and the substrate 12 areelectrically isolated from the semiconductor die 16 by the glue 24and/or the encapsulation layer 30.

The exposed electrical contacts 20 on the second surface 15 of thesubstrate 12, which may be solder balls in a BGA package, facilitateelectrical and/or mechanical coupling of the package 10 to externalcircuitry, such as to an external printed circuit board.

By stacking the semiconductor die 16 over one or more electricalcomponents 14, increased integration of components is provided in thesemiconductor package 10 without increasing the footprint of the package10.

FIG. 2 shows a cross-sectional view of another semiconductor package 110according to one or more embodiments of the present disclosure. Thesemiconductor package 110 shown in FIG. 2 is similar in structure andfunction to the semiconductor package 10 shown in FIG. 1, except for thedifferences that will be discussed below. The features shared by thesemiconductor packages 110 and 10 will not be described herein again inthe interest of brevity.

The main difference between the semiconductor package 110 shown in FIG.2 and the semiconductor package 10 shown in FIG. 1 is that thesemiconductor package 110 does not include the glue 24 encapsulating theelectrical components 14 between the semiconductor die 16 and the firstsurface 13 of the substrate 12. Instead, the semiconductor die 16 isattached to upper surfaces of the underlying electrical components 14 byan adhesive, such as die attach film 124. As an alternative to dieattach film 124, any adhesive, including glue, may be positioned on theupper surfaces of the electrical components 14, and the semiconductordie 16 may be secured to the electrical components 14 by the adhesive.

Further, instead of glue 24 being positioned between neighboringelectrical components 14 that underlie the semiconductor die 16, thespaces between the neighboring electrical components is filled by theencapsulation layer 30 in the semiconductor package 110. This may beaccomplished, for example, by a molding underfill process, in which theencapsulation layer 30, e.g., molding material, is used to bothunderfill and over mold the structure in a same step.

FIG. 3 shows a cross-sectional view of yet another semiconductor package210 according to one or more embodiments of the present disclosure. Thesemiconductor package 210 shown in FIG. 3 is similar in structure andfunction to the semiconductor package 10 shown in FIG. 1, except for thedifferences that will be discussed below. The features shared by thesemiconductor packages 110 and 10 will not be described herein again inthe interest of brevity.

The main difference between the semiconductor package 210 shown in FIG.3 and the semiconductor package 10 shown in FIG. 1 is that thesemiconductor package 210 includes a modified substrate 212 in which acavity 260 is formed. The cavity 260 extends through the first surface213 (e.g., upper surface) of the substrate 212 and defines a thirdsurface 211 that forms a bottom surface of the cavity 260. The thirdsurface 211 is between the first surface 213 and the second surface 215,as shown. That is, the cavity 260 extends only partially into thesubstrate 212.

Another difference is that one or more electrical components 14 arepositioned in the cavity 260. The electrical components 14 areelectrically and mechanically coupled to the substrate 212 in the sameway as discussed above with respect to FIG. 1, e.g., the electricalcomponents 14 may be coupled to respective electrical contacts that areexposed on the surface of the semiconductor die 212. However, due to thecavity 260 in substrate 212, the electrical components 14 that underliethe semiconductor die 16 may be coupled, e.g., by solder paste 22, toelectrical contacts 218 that are exposed on the third surface 211 of thesubstrate 212. That is, the electrical contacts 218 may be formed in thebottom surface of the cavity 260. For example, the substrate 212 may bea multi-layer PCB, and the cavity 260 may be formed through one or moreof the layers, with electrical contacts 218 being exposed in the bottomsurface of the cavity 260. Accordingly, the electrical components 14 inthe cavity 260 may be electrically coupled to the substrate 212 by theelectrical contacts 218 in the cavity 260.

In some embodiments, the electrical components 14, once positioned inthe cavity 260 and electrically coupled to the respective electricalcontacts 218, may extend to a height that is substantially coplanar withthe first surface 213. In other embodiments, the electrical components14 may extend from the third surface 211 to a height that is above orbelow the first surface 213. This may depend on the height of theelectrical components that are selected to be positioned in the cavity260. All of the electrical components in the cavity 260 may have asubstantially same height, which provides a relatively uniform, flatsurface for attaching the semiconductor die 16. However, in someembodiments, the electrical components 14 in the cavity 260 may havevarious different heights.

The electrical components 14 in the cavity 260 may be encapsulated byglue 24, which may substantially fill the cavity 260 and may extendbetween and around the electrical components 14. The semiconductor die16 is positioned on the glue 24 and is mechanically attached to theunderlying electrical components 14 by the glue 24.

Some embodiments do not include the glue 24 encapsulating the electricalcomponents 14 in the cavity 260. Instead, in some embodiments, thesemiconductor die 16 is attached to upper surfaces of the underlyingelectrical components 14 by an adhesive, such as a die attach film orother adhesive, similar to the implementation shown in FIG. 2. In suchembodiments, the spaces between neighboring electrical components 14 inthe cavity 260 may be filled by the encapsulation layer 30 in thesemiconductor package 210.

FIG. 4 shows a cross-sectional view of yet another semiconductor package310 according to one or more embodiments of the present disclosure. Thesemiconductor package 310 shown in FIG. 4 is similar in structure andfunction to the semiconductor package 110 shown in FIG. 2, except thatthe semiconductor package 310 includes spacers 350, which may be solderballs (as shown) or any other pillars or other structure suitable tosupport the semiconductor die 16. The spacers 350 are attached to thefirst surface 13 of the substrate 12, for example, by an adhesive suchas solder paste 22. The spacers 350 may be positioned adjacent to aperiphery of the semiconductor die 16. For example, one or more spacers350 may be positioned under each side edge of the semiconductor die 16.In an example where the semiconductor die 16 is rectangular from a topview, one or more spacers 350 may be positioned below each of four sidesof the semiconductor die 16.

The semiconductor die 16 may be attached to the spacers 350 by anadhesive 124, such as a die attach film, glue, or any other suitableadhesive. The spacers 350 may have a height that is greater than theheights of the electrical components 14 that are positioned between thefirst surface 13 of the substrate 12 and the semiconductor die 16. Thisallows the semiconductor die 16 to be spaced apart from the electricalcomponents 14, which further allows for electrical components 14 ofdifferent types (e.g., resistors, capacitors, inductors, etc.) havingvarying heights to be positioned below the semiconductor die 16, sincethe spacers 350 stably support the semiconductor die 16 rather than theelectrical components 14.

The encapsulation layer 30 may be formed by molding underfill, and maycover the semiconductor die 16, the conductive wires 26, and theelectrical components 14 disposed below the semiconductor die 16, aswell as one or more electrical components 14 disposed on the substrate12 and spaced apart laterally from the semiconductor die 16.

It should be noted that the spacers 350, such as solder balls, are notelectrically coupled to the active surface 17 of the semiconductor die16. Instead, the active surface 17 faces away from the spacers 350 andis electrically coupled only to the substrate 12, e.g., by conductivewires 26. That is, the spacers 350 provide only mechanical support tothe semiconductor die 16, e.g., to support the semiconductor die 16 in aposition that is spaced apart from the substrate 12 and the electricalcomponents 14 underlying the semiconductor die 16.

FIG. 5 shows a cross-sectional view of yet another semiconductor package410 according to one or more embodiments of the present disclosure. Thesemiconductor package 410 shown in FIG. 5 is similar in structure andfunction to the semiconductor package 310 shown in FIG. 4, except thatthe semiconductor package 410 includes a spacer 450 that is positionedbelow a central portion of the semiconductor die 16, as opposed to thespacers 350 positioned near a periphery of the semiconductor die 16 inthe semiconductor package 310.

The spacer 450 may be any structure suitable to support thesemiconductor die 16 in a position that is spaced apart from the firstsurface 13 of the substrate 12. In one or more embodiments, the spacer450 is a dummy die. The dummy die may be, for example, a piece of asemiconductor material such as silicon that is not electricallyconnected to other circuitry in the package 410. For example, the dummydie may not have an active surface or electrical components or circuitryformed in the dummy die. Instead, the dummy die is used in thesemiconductor package 410 only as a mechanical spacer to support thesemiconductor die 16 in a position that is spaced apart from the firstsurface 13 of the substrate 12.

The spacer 450 may be attached to the first surface 13 of the substrate12 by an adhesive 424. The adhesive 424 may be any adhesive materialsuitable to attach the spacer 450 to the first surface 13 of thesubstrate 12, and may be, for example, a glue, a die attach film, or thelike.

The semiconductor die 16 may similarly be attached to an upper surfaceof the spacer 450 by an adhesive 434. The adhesive 434 may be anyadhesive material suitable to attach the semiconductor die 16 to thespacer 450, and may be, for example, a glue, a die attach film, or thelike. The adhesive 434 may be the same material used as the adhesive424, or it may be a different adhesive material. For example, in someembodiments, the adhesive 424 may be glue, while the adhesive 434 may bea die attach film.

The semiconductor die 16 may have a width that is greater than the widthof the spacer 450, as shown. Accordingly, the semiconductor die 16 maybe centered on the spacer 450, and overhang regions 470 are formed wherethe semiconductor die 16 extends outwardly beyond the edges of thespacer 450. In the overhang regions 470, the semiconductor die 16 issuspended over the first surface 13 of the substrate 12.

One or more electrical components 14 may be positioned on the firstsurface 13 of the substrate 12, with the electrical components 14 beingbetween the substrate 12 and the semiconductor die 16 in the overhangregions 470. The lower surface of the semiconductor die 16 and/or theadhesive 434 may be spaced apart from upper surfaces of the electricalcomponents 14 in the overhang regions 470, as shown. Alternatively, oneor more of the electrical components 14 may have upper surfaces that aresubstantially coplanar with the upper surface of the spacer 450, suchthat the spacer 450 as well as one or more of the electrical componentsprovide mechanical support for the semiconductor die 16.

The overhang regions 470 allow for placement of electrical components 14having various sizes between the semiconductor die 16 and the substrate12. That is, since the semiconductor die 16 is supported by the spacer450 (e.g., instead of by the electrical components 14), it does notmatter whether the components 14 have different heights, as the spacer450 provides a uniform, flat surface for mounting the semiconductor die16. Moreover, it does not matter if the electrical components 14 aredistributed in a non-uniform manner below the semiconductor die 16,since the semiconductor die 16 is already stably supported by the spacer450.

Although the various semiconductor packages illustrated in FIGS. 1through 5 are shown as BGA packages, e.g., with an array of solder ballson the underside of the packages, it should be readily appreciated thatin other embodiments, the packages shown in each of FIGS. 1 through 5may be LGA packages, with lands as electrical contacts on the undersideof the packages.

FIGS. 6A-6D are cross-sectional views illustrating various stages of amethod of manufacturing semiconductor packages, such as thesemiconductor package 10 of FIG. 1, in accordance with one or moreembodiments.

As shown in FIG. 6A, electrical components 14 are coupled to a firstsurface 13 of a substrate 12. More particularly, the electricalcomponents 14 have leads or conductive contacts that are electricallycoupled to respective electrical contacts 18 formed on or in the firstsurface 13 of the substrate 12. The electrical components 14 may becoupled to the electrical contacts 18 by a conductive material, such assolder paste 22.

Although not shown, the substrate 12 includes a variety of conductivepaths, such as vias, conductive through-holes, conductive signal pathsor layers and the like, that electrically couple the electrical contacts18 on the first surface 13 to one or more other electrical contacts 18on the first surface and/or to conductive pads on the second surface 15.In one or more embodiments, the substrate 12 may be a multi-layer PCB.

As shown in FIG. 6B, an adhesive, such as glue 24, may be formed over atleast some of the electrical components 14. In particular, the glue 24is formed over a grouping of electrical components 14, shown near themiddle of the structure of FIG. 6B, which will later form a platform formounting the semiconductor die 16. The glue 24 may be, for example, aglob top, which forms an electrically insulating protective dome overthe electrical components 14. The glue 24 may be dispensed on theelectrical components 14 and may form a dome shape, which may beflattened after dispensing, as shown. The glue 24 substantiallysurrounds or encapsulates the electrical components 14.

As shown in FIG. 6C, a semiconductor die 16 is positioned on the glue 24and is mechanically attached to the underlying electrical components 14by the glue 24. The semiconductor die 16 has an active surface 17 thatfaces away from the first surface 13 of the substrate 12.

Conductive wires 26 are formed, e.g., by wiring bonding, between leadsor bond pads on the active surface 17 of the semiconductor die 12 andrespective electrical contacts 18 on the first surface 13 of thesubstrate 12.

As shown in FIG. 6D, an encapsulation layer 30 is formed over thesemiconductor die 16, and covers the semiconductor die 12 and theconductive wires 26. The encapsulation layer 30 may be formed by amolding underfill process, and the encapsulation layer 30 maysubstantially fill any spaces between an upper surface of theencapsulation layer 30 and the first surface 13 of the substrate 12. Insome embodiments, the encapsulation layer 30 may further be provided onside surfaces of the substrate 12 and/or on portions of the secondsurface 15 of the substrate 12.

Also as shown in FIG. 6D, electrical contacts 20 are formed on thesecond surface 15 of the substrate 12, thereby forming a completedsemiconductor package 10. The electrical contacts 20 may be, forexample, solder balls in a BGA package as shown in FIG. 6D. In otherembodiments, the electrical contacts 20 may be lands in a LGA package.In some embodiments, the electrical contacts 20 are pre-formed, or areotherwise formed on the second surface 15 of the substrate 12 prior toplacement of the electrical components 14 on the first side 13 of thesubstrate as shown in FIG. 6A.

The method of manufacturing semiconductor packages illustrated in FIGS.6A-6D may be modified to manufacture the semiconductor package 110 shownin FIG. 2. For example, to manufacture the semiconductor package 110,the formation of glue 24 as shown in FIG. 6B may be omitted. Instead,the semiconductor die 16 may be attached to the upper surfaces of theunderlying electrical components 14 by an adhesive, such as die attachfilm. Further, instead of glue 24 being positioned between neighboringelectrical components 14 under the semiconductor die 16, the spacesbetween neighboring electrical components may be filled by theencapsulation layer 30.

Similarly, the semiconductor packages 310 and 410 shown in FIGS. 4 and5, respectively, may be formed by modified versions of the method shownin FIGS. 6A-6D. In particular, spacers 350 or spacers 450 may bepositioned on the first surface 13 of the substrate 12, for example, ina same step as the electrical components 14 are positioned on thesubstrate 12 shown in FIG. 6A. The formation of glue 24 as shown in FIG.6B may be omitted. Instead, the semiconductor die 16 may be attached toupper surfaces of either the spacers 350 (e.g., to form thesemiconductor package 310) or the spacer 450 (e.g., to form thesemiconductor package 410) by adhesives 124 or 434, respectively. Theconductive wires 26 and the encapsulation layer 30 are formed insubstantially the same manner as previously described.

FIGS. 7A-7C are cross-sectional views illustrating various stages of amethod of manufacturing semiconductor packages including a cavity in thesubstrate, such as the semiconductor package 210 of FIG. 3, inaccordance with one or more embodiments.

As shown in FIG. 7A, a cavity 260 is formed in the substrate 212. Thecavity 260 extends through the first surface 213 (e.g., upper surface)of the substrate 212 and defines a third surface 211 that forms a bottomsurface of the cavity 260. The third surface 211 is between the firstsurface 213 and the second surface 215, as shown. The cavity 260 extendsonly partially into the substrate 212.

One or more electrical contacts 218 are exposed on the third surface 211by the cavity 260. For example, the substrate 212 may be a multi-layerPCB, and the cavity 260 may be formed through one or more of the layers,with electrical contacts 218 being exposed on or in the third surface211 of the cavity 260.

As shown in FIG. 7B, electrical components 14 are electrically andmechanically coupled to the substrate 212, in the cavity 260. Moreparticularly, the electrical components 14 are coupled to respectiveelectrical contacts 218 that are exposed on the third surface 211 of thesemiconductor die 212 in the cavity 260. The electrical components 14 inthe cavity 260 may be coupled, e.g., by solder paste 22, to therespective electrical contacts 218 that are exposed on the third surface211 of the substrate 212. In some embodiments, one or more electricalcomponents 14 are coupled to the first surface 211 of the semiconductordie 212.

The electrical components 14 positioned in the cavity 260 may be sizedsuch that upper surfaces of the electrical components 14 aresubstantially coplanar with the first surface 213 of the semiconductordie 212. In other embodiments, the electrical components 14 may extendfrom the third surface 211 to a height that is above or below the firstsurface 213.

Glue 24 is formed in the cavity 260 and may substantially fill thecavity 260, such that glue 24 covers side surfaces of the electricalcomponents 14 and extends between and around the electrical components14. In some embodiments, the glue 24 may further cover upper surfaces ofthe electrical components 14 in the cavity 260.

As shown in FIG. 7C, a semiconductor die 16 is positioned on theelectrical contacts 14 in the cavity 260 and/or on the glue 24, and thesemiconductor die 16 may be mechanically attached to the underlyingelectrical components 14 by the glue 24.

Some embodiments do not include the glue 24 in the cavity 260. Instead,in some embodiments, the semiconductor die 16 is attached to uppersurfaces of the underlying electrical components 14 by an adhesive, suchas a die attach film or other adhesive. In such embodiments, the spacesbetween neighboring electrical components 14 in the cavity 260 may befilled by the encapsulation layer 30 in the semiconductor package 210.

Conductive wires 26 or wire bonds are formed that couple the activesurface 17 of the semiconductor die 16 to the substrate 212. Forexample, the conductive wires 26 may electrically couple respective bondpads (not shown) on the active surface 17 of the semiconductor die 16 torespective electrical contacts 218 on the first surface 213 of thesubstrate 212.

Electrical contacts 20 are formed on the second surface 215 of thesubstrate 212. The electrical contacts 20 may be, for example, solderballs in a BGA package as shown in FIG. 7C, or in other embodiments, theelectrical contacts 20 may be lands in a LGA package. In someembodiments, the electrical contacts 20 are formed on the second surface215 of the substrate 212 prior to placement of the electrical components14 on the first surface 213 of the substrate 212.

An encapsulation layer 30 is formed over the semiconductor die 16, andcovers the semiconductor die 16 and the conductive wires 26 to form apackage body. The encapsulation layer 30 may be formed by a moldingunderfill process, and the encapsulation layer 30 may substantially fillany spaces between an upper surface of the encapsulation layer 30 andthe first surface 213 of the substrate 212. In some embodiments, theencapsulation layer 30 may further be provided on side surfaces of thesubstrate 212 and/or on portions of the second surface 215 of thesubstrate 212.

The encapsulation layer 30 is an electrically insulating material thatprotects the electrical components 14, semiconductor die 16, conductivewires 26, first surface 213 of the substrate 212, and any otherelectrical components or wiring from damage. In one or more embodiments,the encapsulation layer 30 is a molding compound, which may include, forexample, a polymer resin.

In various embodiments of semiconductor packages provided herein, asemiconductor die is stacked over one or more surface mounted electricalcomponents. The electrical components may serve as pillars for mountingthe semiconductor die, which facilitates better package integration andminiaturization. Additional advantages are achieved by the variousembodiments provided herein. For example, an impedance profile between asemiconductor die and capacitors that are stacked below thesemiconductor die is significantly improved as compared to packageshaving the capacitors positioned along a periphery of a top metal layerof a substrate and spaced apart laterally from the die. This is becausea more direct electrical connection (e.g., a shorter conductive path) ispossible in embodiments where the capacitors are positioned below thedie.

The various embodiments described above can be combined to providefurther embodiments. These and other changes can be made to theembodiments in light of the above-detailed description. In general, inthe following claims, the terms used should not be construed to limitthe claims to the specific embodiments disclosed in the specificationand the claims, but should be construed to include all possibleembodiments along with the full scope of equivalents to which suchclaims are entitled. Accordingly, the claims are not limited by thedisclosure.

1. A semiconductor package, comprising: a substrate having a firstsurface; electrical contacts on the first surface of the substrate; oneor more surface mount electrical components on the first surface of thesubstrate and electrically coupled to the electrical contacts; asemiconductor die on the one or more electrical components, thesemiconductor die having an active surface that faces away from thesubstrate; an adhesive layer on the first surface of the substrate andon the one or more electrical components, the semiconductor die beingspaced apart from the one or more electrical components by the adhesivelayer; and wire bonds that electrically couple the active surface of thesemiconductor die to the substrate.
 2. The semiconductor package ofclaim 1 wherein the adhesive layer is glue, and the glue encapsulatesthe one or more electrical components between the semiconductor die andthe first surface of the substrate.
 3. The semiconductor package ofclaim 1 wherein the one or more electrical components are passiveelectrical components.
 4. The semiconductor package of claim 1 whereinthe substrate includes a second surface opposite to the first surface,the semiconductor package further including an array of solder balls oran array of lands on the second surface of the substrate.
 5. Thesemiconductor package of claim 1, further comprising an encapsulationlayer on the semiconductor die, the wire bonds, and the first surface ofthe substrate.
 6. The semiconductor package of claim 1, wherein: thesubstrate includes a cavity that extends into the substrate from asecond surface of the substrate to the first surface, the first surfacebeing between the second surface and a third surface that is oppositethe second surface.
 7. The semiconductor package of claim 6 wherein theadhesive encapsulates the one or more electrical components between thesemiconductor die and the first surface of the substrate.
 8. (canceled)9. The semiconductor package of claim 6 further comprising anencapsulation layer on the semiconductor die and the second surface ofthe substrate.
 10. The semiconductor package of claim 9 wherein theencapsulation layer extends between neighboring electrical components inthe cavity.
 11. The semiconductor package of claim 6 wherein thesubstrate is a multi-layer printed circuit board (PCB) having aplurality of electrical contacts exposed on the first surface of thesubstrate, and the one or more electrical components are electricallycoupled to the substrate via the exposed electrical contacts.
 12. Asemiconductor package, comprising: a substrate having a first surface;electrical contacts on the first surface of the substrate; one or moresolder balls on the first surface of the substrate; a semiconductor diespaced apart from the substrate by the one or more solder balls, thesemiconductor die having an active surface that faces away from thesubstrate; one or more electrical components on the first surface of thesubstrate and positioned between the semiconductor die and thesubstrate, the one or more electrical components being electricallycoupled to the electrical contacts; an adhesive layer between thesemiconductor die and the one or more electrical components; and wirebonds that electrically couple the active surface of the semiconductordie to the substrate.
 13. The semiconductor package of claim 12 furthercomprising an encapsulation layer on the semiconductor die and the firstsurface of the substrate, wherein the encapsulation layer extendsbetween neighboring electrical components between the semiconductor dieand the substrate.
 14. The semiconductor package of claim 12 wherein theone or more electrical components includes a first electrical componenthaving a first height and a second electrical component having a secondheight that is greater than the first height.
 15. The semiconductorpackage of claim 12 wherein the adhesive layer extends between thesemiconductor die and the one or more solder balls.
 16. A semiconductorpackage, comprising: a substrate having a first surface; electricalcontacts on the first surface of the substrate; a spacer on the firstsurface of the substrate; a semiconductor die on the spacer and spacedapart from the substrate by the spacer, the semiconductor die having anactive surface that faces away from the substrate; one or moreelectrical components on the first surface of the substrate andpositioned between the substrate and the semiconductor die, the one ormore electrical components being electrically coupled to the electricalcontacts; an adhesive layer between the semiconductor die and the one ormore electrical components; and wire bonds that electrically couple theactive surface of the semiconductor die to the substrate.
 17. Thesemiconductor package of claim 16, further comprising an encapsulationlayer on the semiconductor die and the first surface of the substrate,wherein the encapsulation layer extends between the one or moreelectrical components and the spacer, and further extends between theone or more electrical components and the semiconductor die.
 18. Thesemiconductor package of claim 16, wherein the adhesive layer extendsbetween the semiconductor die and the spacer.
 19. A method, comprising:attaching one or more electrical components to a surface of a substrate;electrically coupling the one or more electrical components tocorresponding electrical contacts on the substrate; positioning asemiconductor die on the one or more electrical components, thesemiconductor die having an active surface that faces away from thesurface of the substrate; electrically coupling the active surface ofthe semiconductor die to corresponding electrical contacts on thesubstrate; and forming an encapsulation layer over the semiconductordie, the encapsulation layer extending from the active surface of thesemiconductor die to the surface of the substrate.
 20. The method ofclaim 19, further comprising: forming a cavity in the substrate, whereinthe attaching the one or more electrical components to the surface ofthe substrate includes attaching the one or more electrical componentsto a surface of the cavity, the surface of the cavity being between afirst surface of the substrate and a second surface of the substratethat is opposite the first surface.
 21. The semiconductor package ofclaim 6 wherein the wire bonds are electrically coupled to electricalcontacts on the second surface of the substrate.